1. Field of the Invention
This invention relates in general to semiconductor microtechnologies and, more specifically, to highly integrated semiconductor devices with dynamic random access memory (DRAM) cells each having a trench capacitor and a vertical transistor that works perpendicular to the surface of a semiconductor chip. The invention also relates to methodology for fabrication of semiconductor devices of the type stated above.
2. Description of Related Art
In recent years, DRAM devices employing memory cells each consisting essentially of a single transistor and a single capacitor, also known as “1-transistor/1-capacitor” cells, are becoming denser in integration or “bit-packing” density virtually endlessly. On-chip areas of such memory cells are made smaller once per development of a new generation of products. One basic approach to reducing cell areas is to lower the occupation areas of transistors and capacitors, which make up the cells, respectively.
With regard to cell capacitors, one major problem to be solved is how the required amount of capacitance is achieved while at the same time reducing or minimizing onchip cell areas. To this end, several structures for increasing dielectricities of capacitor insulation films and/or increasing effective or “net” capacitor areas have been developed on a per-generation basis. Regarding cell transistors, attempts have been made to microfabricate for miniaturization such transistors while allowing them to retain planar structures. The currently available microfabrication technologies are principally based on traditional scaling rules, such as employing techniques for reducing source/drain diffusion layer depths and gate insulation film thickness values and/or increasing substrate impurity concentration or density.
To further miniaturize the cell transistors for higher integration in future products, the gate insulation film thickness reduction and substrate impurity concentration enhancement will become inevitable for suppressing unwanted threshold voltage drop-down (called the “short channel” effect) along with channel length shrinkage. However, an increase in substrate impurity concentration would result in an increase in junction current leakage between a substrate and storage nodes, which in turn leads to decreases in data-retaining/holding abilities of memory cells, as suggested for example by T. Hamamoto et al., “Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling,” International Electron Devices Meeting (IEDM) Technical Digest at page 915 (1995).
Additionally, whenever an attempt is made to make gate insulation films thinner, a need is felt to lower word line voltages in order to establish the required withstanding voltage or “anti-breakdown” level of gate insulation films used. For DRAM cell transistors, in order to achieve a high retention for holding stored charges in a capacitor, these are required to offer lower on-state leakage currents than ordinary logic circuits. To do this, the transistors must be set higher in threshold voltage thereof. And, if a word-line voltage is potentially lowered while the cell transistors stay high in threshold voltages, then the amount of a signal as stored into the capacitor can decrease. This gives rise to a risk that DRAM cells degrade in operation margins.
High-density DRAM cell structures capable of avoiding these problems have been proposed until today, one of which is disclosed in U.Gruening et al., “A Novel Trench DRAM Cell with a VERtIcal Access Transistor and BuriEd STrap (VERI BEST) for 4 Gb/16 Gb,” IEDM Tech. Dig., 1999. This trench DRAM cell is arranged so that a capacitor is formed at lower part of a trench defined in a substrate while forming, at an upper part of the trench, a vertically structured transistor with a trench side face as its channel.
See FIG. 37. This diagram depicts a cross-sectional structure of the DRAM cell as taught by the above-identified paper, which is taken along a bit-line direction. A substrate 1 has an underlying buried semiconductive layer of n-type conductivity used for formation of a capacitor C, and an overlying p-type semiconductor layer, in which a transistor Q is to be later formed. A trench 2 is formed in the substrate 1 so as to reach the n-type layer. The capacitor is formed at lower part of this trench 2. The capacitor C has a storage electrode, on which a buried strap 3 is formed in a way integral with the storage electrode.
The buried strap 3 is for use as a node for connection between the capacitor C and its overlying transistor Q. Simultaneously, this strap can also do double-duty as an impurity diffusion source of a diffusion layer 5 of the transistor Q. The buried strap 3 has its top surface coated with an insulative film 4 for use as a “cap” layer. A transistor Q of the vertical structure type is then formed on the trench sidewall over the cap insulation film 4. The vertical transistor Q has a source formed of a diffusion layer 6 in the upper surface of the p-type layer and a drain formed of another diffusion layer 5 as fabricated through impurity diffusion from the buried strap 3.
A word line WL is shown in FIG. 37, which is formed integrally with a gate electrode of the transistor Q. In the case of so-called folded bit line structure, a “pass” word line PassWL of a neighboring cell is disposed in close proximity to the word line WL. In this case the bit line BL is to be contacted with the diffusion layer 6 at a portion laterally adjacent to the pass-word line PassWL.
In this way, the DRAM cell of FIG. 37 is arranged so that the transistor gate electrode is embedded or buried in the substrate to overlie the prior known trench capacitor, thereby achieving formation of the intended vertical transistor by use of substantially the same methodology as that in traditional DRAM cells. With such an arrangement, it is possible to provide the required transistor channel length in a direction along the depth, irrespective of on-chip cell occupation areas. This in turn makes it possible to lessen the onchip cell areas without short-channel effects.
Unfortunately, the advantage of the above-stated DRAM cell structure does not come without accompanying a penalty—the vertical transistor Q can readily vary in channel length through effectuation of etch-back processes. This can be said because the buried strap 3's upper surface position is simply determined by etchback depths at process steps of burying polycrystalline silicon materials. The channel length irregularity can cause a problem as to undesired variation or deviation of transistor characteristics.